The invention relates to a converter and a method for converting an input data packet stream of consecutive data packets into an output data symbol stream of data symbols. The respective data packets of the input data packet stream each include user data in the form of consecutive data symbols, wherein each of the data packets are provided by a plurality of N user channels having respectively different predetermined transmission rates. In the output data symbol stream respectively corresponding data symbols from the individual input data packets are sequentially arranged.
The invention particularly relates to an encoder of a CDMA transmitter, in which such a converter is used to provide the respective data symbols consecutively to a CDMA modulator in which the respective data symbols are convoluted with respective codes (e.g. Walsh-codes) having a length e.g. dependent on the spreading factor provided for each channel in the output data symbol stream. Although the converter can be used independently as to whether or not the data packets from the respective user channels arrive asynchronously or synchronously at the encoder, after the converter a synchronous processing (synchronous with respect to the symbol length of a symbol at the basic transmission rate in the air) of the data is required and preferably different data rates should be supported.
Since the invention generally relates to a transmitter of a CDMA-system and in particular to the encoding, interleaving and modulating units of an encoder unit of the CDMA-system, more specifically to the problem of how a plurality of user channels each having a different transmission rate and sending user data as data packets can be combined into a data symbol stream to be processed and CDMA modulated for all channels at the same time, hereinafter, first a general overview of a base station transmitter of a CDMA-system is described with reference to FIG. 1.
In FIG. 1, ATM-IFC is an ATM interface board, ENC is the channel encoder, interleaver, QPSK selector and time alignment unit; BBTX is the CDMA modulation, spreading and combining unit, BBIF is an interface board, BBRX is the CDMA demodulator and despreader for dedicated channels, DEC is the Viterbi decoder for dedicated channels, BBPA is the random access receiver (including a decoding unit), and DC-FILT is the power supply. Asynchronously arriving data packets are input to the encoder ENC at {circumflex over (2)}. The TRX-DIG unit is a digital pulse shaping filter and digital/analog conversion unit.
FIG. 2 shows the encoder ENC with more details. On a plurality of channels ch-0, ch-1 . . . ch-Nxe2x88x921 a plurality of N users input data packets DP0, DP1 . . . DPNxe2x88x921 of variable length (due to the variable transmission rates TR0, TR1, . . . TRNxe2x88x921) which arrive at the FPGA at {circumflex over (2)} (Field Programmable Gate Array). Essentially, in the encoder ENC in FIG. 2, data for user channels and data for common control channels undergo a convolutional encoding at {circumflex over (6)}, {circumflex over (7)} and essentially serial bit streams are input to the FPGA {circumflex over (3)}, which performs the interleaving, time alignment etc. Data is output to the CDMA modulator (indicated with xe2x80x9cBBTX-boardxe2x80x9d in FIG. 2) from the FPGA {circumflex over (5)}. As explained below, the data of common control channels are input to the digital signal processor DSP {circumflex over (1)}.
As is indicated in FIG. 2, the input data of the user channels ch-0, ch-1, . . . ch-Nxe2x88x921 arrive from the ATM-IFC unit (an asynchronous transfer mode interface unit) in data packets DP0, DP1, DP2 . . . DPNxe2x88x921 asynchronously at the first FPGA {circumflex over (2)}. That is, the transmission of data packets of the respective N user channels ch-0, ch-1 . . . ch-Nxe2x88x921 takes place using an asynchronous transfer method (ATM). As is schematically indicated in FIG. 2, within each frame defined by a frame synchronization clock supplied by a main controller, one single packet of each user channel must be processed, i.e. as is shown in FIG. 2, the user data packets DP0, DP1, DP2, . . . DPNxe2x88x921 arriving asynchronously must be processed in a standard frame period of for example T=10 ms.
In FIG. 2, the DSP at {circumflex over (1)} is a digital signal processor which receives configuration data and data packets for the common control channels, configures FGPAs and processes common control channels to the FPGA {circumflex over (6)}. The ATM packets for dedicated physical channels (DPCH) (=user traffic data) are input to the FPGA {circumflex over (2)} as explained above. The FPGA {circumflex over (3)} is essentially a write means for the interleaver and converter (and the time alignment). {circumflex over (4)} is a memory means for the interleaver and converter (and the time alignment). {circumflex over (5)} is a read means for the interleaver and converter (and time alignment) for providing an output symbol stream to the CDMA modulator. {circumflex over (6)} is a convolutional encoder for common control channels. {circumflex over (7)} is a convolutional encoder for dedicated physical channels. {circumflex over (8)} is a unit for performing a frame buffering for dedicated physical channels. In the unit {circumflex over (8)} some synchronisation of the incoming asynchronous input data bit stream is performed if more than one packet arrives for a single channel within the predetermined frame period. This synchronisation ensures that after the unit {circumflex over (8)} only one respective single packet of all channels is processed within the frame period.
On the basis of the above explanations with respect to FIG. 1 and FIG. 2, FIG. 3-1 shows a principle block diagram of an encoder ENC to illustrate the underlying problem of the invention. In principle, the blocks indicated in FIG. 2 are also present inherently in FIG. 2. FIG. 3-2 shows the processing of data packets from the input to the output of the encoder board in several consecutive frames m, m+1, m+2.
As shown in FIG. 3-1, there are a plurality of users US0, US1 . . . USNxe2x88x921 transmitting data packets DP on respective user channels ch-0, ch-1 . . . ch-Nxe2x88x921. As shown with the time line at 10 ms, 20 ms, 30 ms on the left side in FIG. 3-1 it should be understood that actually the packets DP arrive asynchronously at the encoder ENC. Within each frame interval of e.g. 10 ms one data packet of each channel arrives asynchronously.
As mentioned above, if more than one data packet arrives for a channel within the frame interval then the unit {circumflex over (8)} synchronizes i.e. processes these packets in such a way that only one packet per frame interval and channel is input to a parallel/serial converter P/S and thus to the convolutional encoder CC (unit {circumflex over (7)} in FIG. 2). Hereinafter, it is assumed that always one packet arrives asynchronously per channel and frame interval, either because indeed only one packet arrives or because several packets have been processed in the correct manner by the unit {circumflex over (8)}. The parallel/serial converter P/S shown in FIG. 3-1 is preferably arranged between the units {circumflex over (8)} and {circumflex over (7)} in FIG. 2, i.e. before the convolutional encoder CC as shown in FIG. 3-1. However, completely independent of the location and structure of the parallel/serial converter P/S and the structure of the units {circumflex over (2)}, {circumflex over (3)}, the important aspect is that the convolutional encoder CC (unit {circumflex over (7)} in FIG. 2) receives a serial data bit stream SDBS comprising a single packet of each channel per frame interval. For example, if the units {circumflex over (2)}, {circumflex over (8)}, are already provided with said serial data bit stream SDBS, then the parallel/serial converter is not necessary. Thus, the P/S converter is only one of several possibilities to generate the serial data bit stream (as indicated with the dotted line for the encoder ENC in FIG. 3-1).
As is also shown in FIG. 3-1, each user channel ch-0, ch-1, ch-Nxe2x88x921 has a specific transmission rate TR0, TR1, . . . TRNxe2x88x921. The transmission rate TR of the physical channels relates to the time duration of one symbol on the air interface. Thus, dependent on the transmission rate, the data packets DP respectively comprise a corresponding number of bits according to the physical channel to which they are mapped. For example the slowest channel (having a basic transmission rate) considered in the system may comprise 11 byte per data packet (e.g. for a normal speech channel) or 90 byte per data packet (e.g. for an unrestricted data service like a 64 k bit/s ISDN channel). Therefore, as is schematically illustrated in FIG. 3-1, in fact the asynchronously arriving data packets DP each have a different length; that is, the respective transmission of user data in each channel takes place at different transmission rates (in data bursts). However, within each channel the data packets havexe2x80x94due to the constant transmission ratexe2x80x94a constant length, but arrive asynchronously.
A parallel/serial converter P/S (which is situated outside the base station and which is thus not a part of the encoder) converts a single packet of each channel asynchronously arriving within each frame interval into a serial data bit stream SDBS such that the bits of all the single packets of all channels arriving asynchronously within a single frame interval are now serially arranged within the frame period. That is, while the base station e.g. the unit {circumflex over (8)} ensures that only one packet arrives per channel within the frame interval, the converter P/S arranges their bits serially as shown in FIG. 3-1. In FIG. 3-1, DP0,0, DP1,0, DP2,0 . . . DPNxe2x88x921,0 designate the respective 1-st data packets of channels ch-0, ch-1, ch-2, . . . ch-Nxe2x88x921. Likewise, in the next frame period of 10 ms the data packets DP0,1, DP1,1, DP2,1 . . . DPNxe2x88x921,1 designate the 2-nd data packets of the user channels, which are again sequentially arranged. Whilst the packets arrive asynchronously at the P/S converter, the serial data bit stream SDBS contains all data packets of all channels within a single frame period (sequentially arranged). Thus, the serial data bit stream SDBS contains consecutively arranged data bits from the individual user channels due to the sequential arranging of the data packets.
A convolutional encoder CC known per se in the art performs a convolutional encoding on each bit of the data bit stream SDBS with a predetermined coding rate 1/r and constraint length l. Basically, the convolutional encoder CC outputs r bits for each input bit from the input data packet stream IDPS. Consequently, the output bit stream CCBS from the convolutional encoder CC is 1/r times as long as the serial input data bit stream SDBS (more specifically 1/r times longer as the serial data bit stream SDBS). Typical values for r are r=xc2xd or r=⅓.
The serial bit stream CCBS of increased length output by the convolutional encoder CC is interleaved in an interleaver IL also known as such in the art. Essentially, the sequential bit stream CCBS is written into an interleaving matrix in a horizontal direction and the bits are read out again from the interleaving matrix in a vertical direction. Each packet is interleaved separately and the size of the matrix is always chosen such that all bits of one packet from one channel can be accommodated therein. That is, the respective interleaver matrices are determined, filled, and read out separately for each packet, i.e. N-times during a time interval of e.g. T=10 ms.
The matrices are adapted to the number of bits per packet (which is dependent on the transmission rate), i.e. for each transmission rate there exists a special interleaving matrix. If two channels have equal transmission rate, then they are also interleaved in the same manner.
The output ICBS of the interleaver IL is an interleaved bit stream which is then input to a QPSK modulator. Since the input to the QPSK modulator is a bit stream, the modulator operates as a kind of I, Q selector to select e.g. I, Q bits from the bit stream ICBS (the actual QPSK modulation takes place in the analogue world). This QPSK selection process is necessary, since essentially the CDMA modulator MOD performs a complex convolution (bitwise) on I, Q bits. That is, the QPSK selector/modulator outputs in fact data symbols I, Q as pairs to the CDMA modulator to undergo the CDMA modulation. A QPSK modulator known as such in the art can for example assign a first bit of the interleaved bit stream ICBS to be a I-bit, a second bit to be a Q-bit, the third bit to be a I-bit and so on. Furthermore, it should be noted that the QPSK modulator can output the I, Q bits respectively serially or parallely. That is, the QPSK modulator may output two separate bit streams in parallel each containing the I, Q bits respectively.
Whilst the input channels ch-0, ch-1, . . . ch-Nxe2x88x921 can be viewed by the mobile radio network as xe2x80x9clogical channelsxe2x80x9d, the input data symbol stream ODSS input to the CDMA modulator MOD and containing the sequential data symbols can be regarded as xe2x80x9cphysical channelsxe2x80x9d, as indicated in FIG. 3-1. Furthermore, regarding the input to the CDMA modulator, it is in fact irrelevant how the data symbol stream ODSS is obtained, since the CDMA modulator will merely take the individual data symbols to perform the CDMA modulation on them individually. That is, different convolutional encoding schemes or interleaving schemes may be used in the encoder CC and in the interleaver IL or even in the QPSK modulator (the QPSK selector) without any loss of generality. The important issue is, that the CDMA modulator is provided with a data symbol stream ODSS consisting of complex symbols having a real part I and an imaginary part Q, since in the CDMA modulator a complex convolution is performed. Thus, it is irrelevant whether the complex symbol is obtained via a QPSK (QPSK: Quadrature Phase Shift Keying) or via a 16-QAM modulation (selection). Whilst the data bit stream SDBS input to the convolutional encoder CC is packet oriented, the bit streams CCBS, ICBS input to the and output from the interleaver IL are bit-orientated (but still in packets) and the data symbol stream ODSS from the QPSK modulator is data symbol oriented. Therefore, a data symbol rate of the physical channel can for example be 32 ksps, 64 ksps, or 128 ksps (ksps: kilo symbols per second) whilst the logical channels may have a bit rate of e.g. 9.6 kbit/s, 64 kbit/s or 384 kbit/s. Essentially, the symbol rate is adapted to the requirements of the CDMA modulator and the input data rates have to be converted to the physical channel symbol rate by a channel encoding and rate matching process.
FIG. 3-2 summarizes the processing of the data packets in a frame-wise consideration. While in frame m the data packets are input serially to the encoder, in frame m+1 the data packets are serially processed and in frame m+2 the processed data packets having time offsets to each other and with respect to the common (frame) synchronization signal are output in parallel to the CDMA modulator.
Since the CDMA modulator MOD can not handle the user data for one channel in packet form, a convolutional encoding, interleaving and QPSK modulation must provide the user data symbolwise to the CDMA-modulator unit MOD with the respective symbols of all channels which need to be combined at the CDMA modulator output.
Even if only user channels of the same transmission rate are to be handled, the encoder ENC having a structure as shown in FIG. 3-1 requires a conversion, because due to the serial processing of the packets alwaysxe2x80x94i.e. independent of the ratexe2x80x94first all symbols of the first user, then all symbols of the second user, . . . , and finally all symbols of the N-th user arrive sequentially. However, the CDMA modulator MOD requires for its processing at first the first symbols of all packets (i.e. the first symbol from channel ch-0, the first symbol of channel ch-1, . . . the first symbol of channel ch-Nxe2x88x921), then the second symbols of all packets, . . . etc. in a sequential order, i.e. the CDMA modulator requires to be provided with the symbols that need to be combined at the CDMA modulator output at the same time. Due to interface limitations, these symbols (to be combined) themselves are transmitted serially from the encoder ENC to the CDMA modulator.
Moreover, if the kind of system in FIG. 3-1 is to be used for respective user channels having different transmission rates, the data symbol stream ODSS may also containxe2x80x94despite the different transmission ratesxe2x80x94one data symbol of the first channel, four symbols of a second channel and two symbols of a third channel, if the first channel has a basic transmission rate, the second channel has four times the basic transmission rate and the third channel has twice the basic transmission rate.
That is, as shown in the above table 1 (showing the sequence of symbols for 3 different channels in one period 1/TRB) with respect to one time interval 1/TRB (TRB: basic transmission rate of the slowest channel), at least one symbol of each channel is provided. Transmitted are only the bold-faced symbols, which the CDMA modulator MOD will then repeat. This process essentially performs a prespreading to the highest possible symbol rate in the system. As explained above, the CDMA modulator MOD needs at the same time all corresponding symbols, which are to be combined in the next interval of 1/TRB.
Therefore, a first object of the invention is
to provide a converter and a conversion method, which allow to convert the asynchronously arriving data packets into a data symbol stream, which provides in a predetermined time interval, i.e. in the duration of a symbol of the lowest symbol rate on the air interface, one or more symbols for all channels to the CDMA modulator to be spreaded, weighted and combined within this interval.
A second object of the invention is
to provide a converter and a method for providing such a data symbol stream when the input user channels have mutually different transmission rates.
The above objects are solved according to claim 1 by a converter for converting an input data packet stream of consecutive data packets each data packet including user data in the form of a predetermined number consecutive data symbols, from a plurality of N user channels, each user channel having a predetermined transmission rate TR0, TR1, TR2, . . . ,TRn, . . . ,TRNxe2x88x921, being defined as a basic transmission rate TRB or an integer multiple TRn=Kn*TRB thereof, into an output data symbol stream in which a respective number Kn of data symbols of each data packet are sequentially arranged, comprising a memory means having a number of columns and a number of rows, a write means for writing the data symbols of said consecutive data packets into said memory means, such that the data symbols of a data packet having the basic transmission rate TRB are consecutively arranged in one row and the data symbols of data packets having an integer multiple TRn=Kn*TRB of the basic transmission rate TRB are arranged consecutively as sets of Kn consecutive data symbols in respective column portions of Kn rows, and a read means for providing said output data symbol stream by reading said data symbols from the memory means sequentially in the column direction, whereby whenever all TR0/TRB+TR1/TRB+ . . . +TRn/TRB+ . . . TRNxe2x88x921/TRB=K0+K1 . . . +Kn . . . +KNxe2x88x921 data symbols of one column are read out in a time interval of 1/TRB, the reading is continued in the next column at the first row position.
Furthermore, the above objects are solved according to claim 11 by a method for converting an input data packet stream of consecutive data packets each data packet including user data in the form of a predetermined number consecutive data symbols, from a plurality of N user channels, each user channel having a predetermined transmission rate TR0, TR1, TR2, . . . ,TRn, . . . ,TRNxe2x88x921, being defined as a basic transmission rate TRB or an integer multiple TRn=Kn*TRB thereof, into an output data symbol stream in which a respective number Kn of data symbols of each data packet are sequentially arranged, comprising the steps of providing a memory means having a number of columns, writing the data symbols of said consecutive data packets into said memory means, such that the data symbols of a data packet having the basic transmission rate TRB are consecutively arranged in one row and the data symbols of data packets having an integer multiple TRn=Kn*TRB of the basic transmission rate are arranged consecutively as sets of Kn consecutive data symbols in respective column portions of Kn rows, and reading said data symbols from the memory means sequentially in the column direction, whereby whenever all TR0/TRB+TR1/TRB+ . . . +TRn/TRB+ . . . TRNxe2x88x921/TRB=K0+K1 . . . +Kn . . . +KNxe2x88x921 data symbols of one column have been read out in a time interval of 1/TRB, the reading is continued in the next column at the first row position, in order to provide said output data symbol stream.
According to one aspect of the invention the converter contains a memory means having a predetermined number of columns and rows and a write means writing the data packets (consisting of sequentially arranged data symbols) into the memory such that the data symbols of the packet from the user channel having the lowest basic transmission rate TRB will occupy one row in the memory. If more data symbols of a packet from a user channel having an integer multiple TRn=Kn*TRB of the basic transmission rate are to be stored, the data symbols of such a packet are also written in the row direction, however, this being done over a plurality of Kn rows. The writing in of the sequential data symbols of the packet from the higher transmission rate channel is performed in such a way, that the data symbols are consecutively ordered in the column direction. A read means reads out the memory in the column direction andxe2x80x94since the data symbols of packet having higher user rates are sequentially arranged in the column directionxe2x80x94the read out in the column direction will provide the desired output data symbol stream, in which the respective number of data symbols for each packet are sequentially arranged.
This object is also solved by a converter according to claims 19, 20 and 21 and by a method according to claims 22-25.
According to another aspect of the invention, the write means performs the writing in dependent on a clock signal which indicates the switching to a new row dependent on the number of data symbols contained in each packet for each channel. Therefore, each row in the memory can be assigned to a particular channel andxe2x80x94since the transmission rate per channel is constantxe2x80x94the same data symbols are always written into the same rows.
According to another aspect of the invention, the read out means performs the reading out in the column direction depending on a second clock signal which indicates when the reading out should be stopped in one column and should be continued in the next column. Preferably, the second clock signal is determined by the internal timing of the CDMA modulator. Preferably the second clock is the duration of a symbol of the lowest rate in the air (e.g. 1/TRB=1/32 KHz≈31 s). That is, since the CDMA modulator aims at parallely coding all corresponding data symbols of all data packets at a certain timing (after sequentially reading out the data symbol in the column direction from the memory), the CDMA modulator comprises, because of the parallel processing, for each physical channel a separate CDMA modulator unit which then picks out the respective data symbols for each channel from the data symbol stream.
According to another aspect of the invention, the converter according to the invention, when being used in an encoder ENC of a CDMA transmitter, performs the function of the interleaving and the QPSK modulation simultaneously with the conversion of the input stream to the output stream. In this case, the data symbols are stored symbol-wise at each entry in the memory of the converter, wherein the respective bits forming one data symbol are selected from the bit stream output by the convolutional encoder. The writing into the memory of the converter and the reading from the memory of the converter is performed such that the interleaving is achieved at the same time.
Further advantageous embodiments and improvements of the invention are listed in the dependent claims. Hereinafter, the invention will be described with reference to its embodiments and by referring to the attached drawings.